1. Field of the Invention
The present invention relates to a data access device for a DRAM and, more particularly, to an access device having a reduced layout and increased accessing speed.
2. Discussion of Related Art
In general, during the sensing operation of a DRAM, cell data is transmitted to a bit line after a word line is actuated by a signal generated by a row decoder. The cell data transmitted to the bit line is then sensed by a sensing amplifier. The output ports of the sensing amplifiers are commonly connected to a data bus, and an amplifying array for outputting data is connected to an end of the data bus. FIGS. 1 and 2 illustrate two conventional data accessing devices using this technique.
As illustrated in FIG. 1, a conventional data access device of a DRAM includes first to nth bit line sensing amplifiers BS1-BSn for amplifying a signal applied to a bit line which controls a column of a memory matrix; first to nth decoders Y1-Yn for receiving first to nth code signals YC-YCn, respectively, and a pulse signal YP, and for generating a selection output according to those two signal inputs; a plurality of column sensing amplifiers CS1 through CSn for connecting the output signals of the first to nth sensing amplifiers BS1 to BSn (namely, the data output from a memory cell) with first and second data buses DBa and DBb according to the state of the selection output signals from the first to nth decoders Y1 to Yn; and a data amplifier DS, connected to the ends of the first and second data buses DBa and DBb, amplifying the data loaded on the first and second data buses DBa and DBb.
Each of the first to nth decoders Y1 to Yn has the same structure. For example, the first decoder Y1 includes a NAND gate 10 for receiving an externally input first code signal YC1 and a pulse signal YP, and performs a NAND logic operation thereon. Each of the first to nth decoders Y1-Yn receives the pulse signal YP, but a different code signal.
A CMOS inverter 20 receives and inverts the output of the NAND gate 10. The CMOS inverter 20 includes a PMOS transistor MP and an NMOS transistor MN. The drain and source of the NMOS transistor MN are connected to the drain of the PMOS transistor MP and ground, respectively. The source of the PMOS transistor MP is connected to a reference voltage VINT, and the gates of the PMOS and NMOS transistors MP and MN are connected to the output of the NAND gate 10. The connection between the drains of the PMOS and NMOS transistors MP and MN serves as the output for the first decoder Y1.
Each of the column sensing amplifiers CS1 to CSn has the same structure. The first column sensing amplifier CS1, for example, includes first and second NMOS transistors N1 and N2, having their gates connected to the output of the first decoder Y1, and third and fourth NMOS transistors N3 and N4, having their gates connected to bit and inverse bit lines BO NMOS transistors N3 and N4, having their gates connected to bit and inverse bit lines BO and BbO of the first bit line sensing amplifiers BSa1. The drains of the first and second NMOS transistors N1 and N2 are connected to the first and second data buses DBa and DBb, respectively. The sources of the first and second NMOS transistors N1 and N2 are connected to the drains of the third and fourth NMOS transistors N3 and N4, respectively, and the sources of the third and fourth NMOS transistors N3 and N4 are connected to ground.
The thus-structured conventional device operates as follows. When the first decoder Y1 outputs a signal having a logic high state based on the pulse input YP and the first code signal YC1, the second to nth decoders Y2-Yn output signals having a logic low state. The second to nth code signals YC1-YCn are generated such that only one of the first to nth decoders Y1-Yn outputs a logic high signal. Namely, only one of the first to nth code signals YC1-YCn has a logic high state, and the corresponding one of the first to nth decoders Y1-Yn will output a logic high signal when the pulse signal YP achieves a logic high state.
Particularly, the operational procedure of the first decoder Y1 is as follows. If the first decoder Y1 is not selected initially, the first code signal YC1 maintains the logic low state so that the output signal of the NAND gate 10 is logic high. Therefore, the output signal of the inverter 20 is logic low. Even if the pulse signal YP is logic high, as long as the first code signal YC1 is logic low, the output signal of the NAND gate 10 is logic high and the output of the inverter 20 is logic low. Thereafter, if the pulse signal YP and the first code YC1 are both logic high, the output of the NAND gate 10 goes low. The output of the inverter 20 thus becomes logic high. Because the output signal of the first decoder Y1 and N2 of the first column sensing amplifier CS1 turn on, and the voltages of the bit and inverse bit lines BO and BbO read out of the cell are transmitted to the first and second data buses DBa and DBb.
Specifically, one of the bit and inverse bit lines BO and BbO will have a logic high state such that a corresponding one of the third and fourth NMOS transistors N3 and N4 will turn on. As a result, the one of the first and second data buses DBa and DBb connected to the one of the third and fourth NMOS transistors N3 and N4 which is on will be pulled to ground (i.e., logic low). The other of the first and second data buses DBa and DBb remains at a pre-charged logic high state. The data amplifier DS amplifies the voltage difference on the first and second data buses DB and DBb.
FIG. 2 illustrates another conventional data access device. The conventional data access device of FIG. 2 is the same as the data access device of FIG. 1, except for the structure of the column sensing amplifiers. Therefore, only the structure and operation of first to mth column sensing amplifiers CS1-CSm will be described. Each of the first to mth column sensing amplifiers CS1-CSm is identically structured.
As shown in FIG. 2, the first column sensing amplifier CS1 includes first and second NMOS transistors N0 and N1 having their gates connected to the output of the first decoder Y1. The sources of the first and second NMOS transistors N0 and N1 are connected to the first and second data buses DBa and DBb, respectively, while the drains of the first and second NMOS transistors N0 and N1 are connected to the bit and inverse bit lines BO and BbO, respectively.
When the output of the first decoder Y1 is logic high, the first and second NMOS transistors N0 and N1 turn on such that the first and second data buses DBa and DBb assume the logic state of the bit and inverse bit lines BO and BbO, respectively.
The above-mentioned conventional devices have no specific operational problem. But, as DRAMS become more highly integrated, the size of a cell decreases; and therefore, the limitation of the bit line's width for reading out the cell's data also reduces. As a result, it gets more difficult to arrange the bit line sensing amplifier and the corresponding column sensing amplifier. In addition, when the voltage difference between the data bit and the inverted data bit on the first and second data buses DBa and DBb is great, the sensing operation is easily performed by the data amplifier DS, but, it takes too much time to equalize the voltages on the data buses after the sensing operation and in preparation for the next sensing operation. Therefore, the accessing speed of the entire memory is slow.